1. Field of the Invention
The present invention relates to a high-withstand-voltage semiconductor device using a multiple floating field-plate (MFFP) and, more particularly, to a semiconductor device which can be designed to have an increased withstand voltage.
2. Background Art
High-voltage ICs (HVIC) are being used for gate control on power semiconductors, e.g., an IGBT mounted in an inverter. Some HVICs have low-side and high-side gate drive circuits and a logic circuit for control incorporated in one chip. Also, an HVIC incorporating a high-withstand-voltage level shifter (semiconductor device) using a multiple floating field-plate (MFFP) for driving a high-side IGBT gate has been proposed (see, for example, Japanese Patent Laid-Open No.2005-251903 or pp-379 to 382 of ISPSD 2004).
FIG. 11 is a plan view showing a conventional semiconductor device. FIG. 12 is a sectional view taken along line F-F′ in FIG. 11.
An n-type semiconductor layer 12 is epitaxially grown on a p-type semiconductor substrate 11. An n+-type drain region 13 is provided in an upper surface of the semiconductor layer 12 substantially at a center of a region in which a MOS transistor 102 is disposed. An n−-type buried layer 14 and an n+-type buried layer 15 are provided at the interface between the semiconductor layer 12 and the semiconductor substrate 11 below the drain region 13. A back electrode 16 is connected to a lower surface of the semiconductor substrate 11. The back electrode 16 is grounded.
A p-type impurity region 17 is formed in the upper surface of the semiconductor layer 12 separately from the drain region 13 so as to surround the drain region 13. An n+-type source region 18 is provided in the upper surface of the impurity region 17 so as to surround the drain region 13.
A field oxide film 19 is provided on the semiconductor layer 12 between the impurity region 17 and the drain region 13. A gate electrode 20 and first field plates 22a to 22d and 23 are provided on the field oxide film 19. The gate electrode 20 and the first field plates 22a to 22d and 23 are orderly placed along a direction from the source region 18 toward the drain region 13 by being spaced apart one from another. The gate electrode 20 and the first field plates 22a to 22d and 23 surround the drain region 13 so that the drain region 13 is centered in the configuration of the gate electrode and the field plates as viewed in plan. The first field plates 22a to 22d and 23 are floating electrodes insulated from portions existing on the peripheries thereof.
The gate electrode 20 also extends from the field oxide film 19 to the impurity region 17 and covers an end portion of the impurity region 17 interposed between the source region 18 and the semiconductor layer 12, with a gate oxide film 21 interposed between the gate electrode 20 and the end portion of the impurity region 17. The first field plate 23 extends from the field oxide film 19 to the drain region 13 and covers an end portion of the drain region 13 without contacting the same.
Above the semiconductor layer 12 and the field oxide film 19, an insulating film 24 covers the gate electrode 20 and the first field plates 22a to 22d and 23. A source electrode 25 is electrically connected to the impurity region 17 and the source region 18 by being extended through the insulating film 24. A drain electrode 26 is electrically connected to the drain region 13 by being extended through the insulating film 24.
Second field plates 27a to 27e are provided on the insulating film 24. The second field plates 27a to 27e are floating electrodes insulated from portions existing on the peripheries thereof. The second field plates 27a to 27e are orderly placed respectively above gaps between the gate electrode 20 and the first field plates 22a to 22d and 23 along a direction from the source region 18 toward the drain region 13 by being spaced apart one from another. The second field plates 27a to 27e are placed so that each second field plate overlaps, as viewed in plan, end portions of the corresponding two first field plates adjacent to each other and located below the second field plate. The second field plates 27a to 27e have cut portions in a region through which a high-voltage wiring conductor 28 described below extends. The second field plates 27a to 27e surround the drain region 13 generally on the entire periphery of the same as viewed in plan except at the cut portions.
The high-voltage wiring conductor 28 is provided on the insulating film 24 to electrically connect an external high-potential logic circuit 101 and the drain electrode 26 to each other. The high-voltage wiring conductor 28 extends over the gate electrode 20 and the first field plates 22a to 22d and 23. The high-voltage wiring conductor 28 is spaced apart from the second field plates 27a to 27e. 
The first field plate 23 is electrostatically coupled to the upper surface of the drain region 13. The gate electrode 20 functions as a field plate, and the gate electrode 20 and the first field plates 22a to 22d are electrostatically coupled to each other and also to the upper surface of the semiconductor layer 12. Electric field concentration on the upper surface of the semiconductor layer 12 based on the potential difference between the drain region 13 and the source region 18 can be reduced by the above-described electrostatic coupling.
In the above-described conventional semiconductor device, however, the potential on the first field plates 22a to 22d and 23 which need to have a lower potential is increased under the influence of the high-voltage wiring conductor 28, to which a high voltage of several hundred volts is applied. In particular, the influence on the first field plate 22a which is positioned closest to the source side and which needs to have the lowest potential is large. Electric field concentration therefore occurs in the vicinity of the upper surface of the semiconductor layer 12, so that the extension of a depletion layer is limited and the withstand voltage is reduced.